A complex question and a simple answer
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What the heck!
“It’s so simple to be wise. Just think of something stupid to say and then don’t say it.”
But I always say.. 
SOC aur mein, abhie abhie :)
Wow, I registered a project for the google summer of code. And for those who know how lazy I am, don’t be surprised, it’s also my academic main project! (I have no other way but to do it) The proposal was written today afternoon at about 3.00 pm and didn’t spend much time over it as I need to send it today itself (it was supposed to be the final day for accepting proposals; they postponed it to 26th now). Pramode Sir verified it and added some points more. And the mentor organization under which the project goes is ‘The Free software initiative of Japan”. Internet is an amazing technology – just after an hour I had a comment from the Japanese mentor team, asking about the project. (The project is not yet approved by the SOC people :D)
Earlier today I was busy preparing my seminar report and that was a really dumb job. I was trying each and every magical spells I know to find out those materials I collected at the time of seminar. Anyways, the whole report is ready to be submitted now.
Ah, had a late night call from Sujith from Bangalore. He is a real nice friend, he talked about half an hour to me and stopped just because I told him to and I am sure he does the same with his other friends. Dude, money does matters. He was totally excited about the talk he delivered in BMC College, Bangalore. This excitement person like Sujith express is one of the greatest motivational catalysts for me.
And to Sandhya, this is the question I promised to tell you (found it somewhere in the net) :
Sort an array which represents a binary search tree in least time complexity (say O(n)).
(Well, this is another technique to increase my hit count! I can now tell her to check my blog for the question :P)
Latest Realization
My heart has two auricles and two ventricles…..
Verilog - ing
Verilog is a hardware description language (HDL) that one could easily learn and use because it looks like C language in syntax – the control flow statements like if and while, language operators and their precedence etc are similar to that of C. The language differs from the conventional programming language as the execution of statements is not strictly linear. Oh!! I forget to tell what a HDL is.. HDL is any language used for the formal description of electronic circuits. It describes the circuits operation and through simulations we can check if the circuit is behaving as we intend. With that the formal introduction of this article ends. Now let us do some Verilog-ing.
As a first step one need to design the circuit and then he has to decide how to use Verilog to describe it. For the time being let me focus on gate level modeling.
X = AB + C :: this is what I want to simulate using Verilog. The operation can be implemented using a single AND gate and an OR gate.
W0 is the wire where we get ‘a’ AND ‘b’ which is ORed with ‘c’ to get ‘x’. Now the circuit can be described by Verilog as follows:
module fun(a,b,c,out);
input a,b,c;
output out;
wire w0;
and(w0,a,b);
or(out,w0,c);
endmodule
The Verilog design consists of hierarchy of modules. Modules are defined and then instantiated in other modules. Module is defined using the keywords module and endmodule. Following the keyword module is the user defined module name, followed by a list of signals. Signals are interface of the module to other modules (think them as ports). Each port can be defined as input, output, inout etc… Another type called “wire” is used to define signals used to make simple connections between basic elements – in this case w0.
Next we have the body of the module. Verilog predefines AND, OR, NOT, NAND, NOR, XOR, XNOR and BUF. The convention for built-in gates is that their output signal is first port and the remaining ports are input.
Anything written after // is a comment as in the case with C.
Before using this module within other modules we need to test if everything is working according to our wish. In Verilog it’s a common practice to define a special module without any ports to test another module. It is commonly referred to as testbench. The following module represents a testbench for the module fun.
module test;
reg l,m,n;
reg expected;
wire f;
fun test_fun(.a(l),.b(m),.c(n),.out(f));
initial
begin
#0 l=0;m=0;n=0;expected=0;
#10 n=1;expected=1;
#10 m=1;n=0;expected=0;
#10 n=1;expected=1;
#10 l=1;m=0;n=0;expected=0;
#10 n=1;expected=1;
#10 m=1;n=0;expected=1;
#10 n=1;expected=1;
#10 $finish;
end
initial
$monitor(”a=%b b=%b c=%b out=%b, expected out=%b time=%d”, l,m,n,f,expected,$time);
endmodule
You can see assignment statements within the body of module test. This is a way to set a signal to a particular logic value at a particular time. The left hand side of assignments should be of type ‘reg’.
The fourth line is where we instantiate module fun with a local name test_fun. What follows is a list of connections between our local signals and the ports of module fun each one preceded by a ‘.’.
The initial keyword says that everything in the following block should be done at the start of simulation. The “#” followed by a number denote the time at which that statement is to be executed. The first statement will be executed at 0ns from the time of simulation, the second at 10ns from previous, etc… And the simulation ends with $finish.
The last step is to do something so that we could observe the simulation. For this we use another “initial” block which uses a special built-in function named $monitor which watches the signals that are connected to it and prints out whenever any one of them change. “%b” denotes that the number is represented in binary and “%d” for decimal. The simulation time is obtained from $time
This is what we get when we run the program
a=0 b=0 c=0 out=0, expected out=0 time= 0
a=0 b=0 c=1 out=1, expected out=1 time= 10
a=0 b=1 c=0 out=0, expected out=0 time= 20
a=0 b=1 c=1 out=1, expected out=1 time= 30
a=1 b=0 c=0 out=0, expected out=0 time= 40
a=1 b=0 c=1 out=1, expected out=1 time= 50
a=1 b=1 c=0 out=1, expected out=1 time= 60
a=1 b=1 c=1 out=1, expected out=1 time= 70
That looks cute, right?
Heading for FOSS.NIT
Not much of preparation for tomorrow’s trip to kozhikode for attending FOSS.NIT. At this point I am really excited to travel with Pramode sir and to watch his show (magic with Phoenix and the robot) at NIT. Anjali had her permission from her parents today and will be coming with us. And of course there is Anish and Shaleena from our class (the real FOSS people of GEC). Three of my juniors (Krishnanunni, Sreeraj, Anil), the members of dhanush team and the representative of Electronics department, Naveen makes the whole team set for the trip.
NIT is National Institute of Technology so there would be students from all over the nation, right? There should be students from north India studying out there. Hope I could have some real OPEN SOURCE fiesta out there 
… Some of my friends out there in NIT had given me a lot of promises.
I found out an advantage of having guest lecturers today. I could listen in a much better way to Sminesh sir’s class (he is a permanent staff and is knowledgeable) now.
And to Leya: You will repent once for what you said today :-X.
Exhausted :(
Just completed the assignment I have to submit tomorrow (Wah, 31 pages!!!!). I thought of watching the video ‘The divine healing’ given to me by Piyush today and he has his reasons for that. He said if I am really searching for truth then the video could transform me (transform me to a believer… he thinks I am an atheist :p).. Well, I am not in a mood right now to get transformed so will see that tomorrow..
Back to the topic:
For the first time I heard a madam telling that she don’t mind us copying from others (the assignment) and what she demands is 15 sheets of papers stapled together (Well, she didn’t mention how many words per page .. muhaha). The new era of Guest lecturers would kill the department for sure. One of my friends who don’t know that an IC chip requires a Vcc and a GND for it to work is a teacher now (this is true) and another friend (?) who is his student told me how terrible his class is. What is the point in having classes by these teachers- it is much better to leave us free, right?
Now what hurts me the most is that some of them don’t even mind, people copying for exams and it seems like there is mark for the elegancy in copying.
“Our lives begin to end the day we become silent about things that matter.”
